Sixth International Workshop on FPGAs for Software Programmers (FSP 2019) September 12, 2019, Barcelona, Spain co-located with International Conference on Field Programmable Logic and Applications (FPL)
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Like the first four editions, the Fifth International Workshop on FPGAs for Software Programmers (FSP) is co-located with the International Conference on Field-Programmable Logic and Applications (FPL). Therefore, it has moved to Dublin for 2018. As in previous years, FSP continues the publication of its results in IEEE Xplore-indexed proceedings for better visibility. This led to an increased number of 18 submissions (from ten countries). This years proceedings were enabled by the kind sponsorship of Xelera Technologies GmbH. As before, the key focus of FSP 2018 remains on looking at key aspects of using FPGA-based reconfigurable computing from a software developer's perspective. Contributions include not only the presentation of solutions, but also studies on the precise nature of the difficulties to guide further research. Furthermore, FSP is keen to maintain its workshop nature: It remains a venue for presenting not just mature research, but also exposing promising work-in-progress or prototype reports to a wider community for inspiring scientific discourse. In this spirit, based on recommendations by the Program Committee, the FSP Chairs selected six submissions (33 %) to be presented as full papers, and three (17 %) as posters. These cover a wide range of topics, ranging from analysis and transformation tools to applications and frameworks for High-Level Synthesis. The Chairs would like to thank the Program Committee for their timely reviews, enabling us to base our decisions on at least three reviews per submission. Presented at the workshop itself were two keynotes from industry, as well as three regular paper sessions and a poster session.

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The aim of this workshop is to make FPGA and reconfigurable technology accessible to software programmers.Despite their frequently proven power and performance benefits, designing for FPGAs is mostly an engineering discipline carried out by highly trained specialists.With recent progress in high-level synthesis, a first important step towards bringing FPGA technology to potentially millions of software developers was taken. The FSP Workshop aims at bringing researchers and experts from both academia and industry together to discuss and exchange the latest research advances and future trends.This includes high-level compilation and languages, design automation tools that raise the abstraction level when designing for (heterogeneous) FPGAs and reconfigurable systems and standardized targetplatforms.This will in particular put focus on the requirements of software developers and application engineers.In addition, a distinctive feature of the workshop will be its cross section through all design levels, ranging from programming down to custom hardware.Thus, the workshop is targeting all those who are interested in understanding the big picture and the potential of domain-specific computing and software-driven FPGA development.In addition, the FSP Workshop shall facilitate collaboration of the different domains. Topics of the FSP Workshop include, but are not limited to: • High-level synthesis (HLS) and domain-specific languages (DSLs) for FPGAs and heterogeneous systems • Mapping approaches and tools for heterogeneous FPGAs • Support of hard IP blocks such as embedded processors and memory interfaces • Development environments for software engineers (automated tool flows, design frameworks and tools, tool interaction) • FPGA virtualization (design for portability, resource sharing, hardware abstraction) • Design automation technologies for multi-FPGA and heterogeneous systems • Methods for leveraging (partial) dynamic reconfiguration to increase performance, flexibility, reliability, or programmability • Operating system services for FPGA resource management, reliability, security • Target hardware design platforms (infrastructure, drivers, portable systems) • Overlays (CGRAs, vector processors, ASIP- and GPU-like intermediate fabrics) • Applications (e.g., embedded computing, signal processing, bio informatics, big data,database acceleration) using C/C++/SystemC-based HLS, OpenCL, OpenSPL, etc. • Directions for collaborations (research proposals, networking, Horizon 2020), 14.0 cm x 12.4 cm x 0.5 cm mm, Software.

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